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vnp10n07 "omnifet": fully autoprotected power mosfet september 2013 1 2 3 to-220 block diagram type v clamp r ds(on) i lim vnp10n07 70 v 0.1 w 10 a n linear current limitation n thermal shut down n short circuit protection n integrated clamp n low current drawn from input pin n diagnostic feedback through input pin n esd protection n direct access to the gate of the power mosfet (analog driving) n compatible with standard power mosfet n standard to-220 package description the vnp10n07 is a monolithic device made using stmicroelectronics vipower technology, intended for replacement of standard power mosfets in dc to 50 khz applications. built-in thermal shut-down, linear current limi- tation and overvoltage clamp protect the chip in harsh enviroments. fault feedback can be detected by monitoring the voltage at the input pin. 1/11
absolute maximum rating symbol parameter value unit v ds drain-source voltage (v in = 0) internally clamped v v in input voltage 18 v i d drain current internally limited a i r reverse dc output current -14 a v esd electrostatic discharge (c= 100 pf, r=1.5 k w ) 2000 v p tot total dissipation at t c = 25 o c50w t j operating junction temperature internally limited o c t c case operating temperature internally limited o c t stg storage temperature -55 to 150 o c thermal data r thj-case r thj-amb thermal resistance junction-case max thermal resistance junction-ambient max 2.5 62.5 o c/w o c/w electrical characteristics (t case = 25 o c unless otherwise specified) off symbol parameter test conditions min. typ. max. unit v clamp drain-source clamp voltage i d = 200 ma v in = 0 607080 v v clth drain-source clamp threshold voltage i d = 2 ma v in = 0 55 v v incl input-source reverse clamp voltage i in = -1 ma -1 -0.3 v i dss zero input voltage drain current (v in = 0) v ds = 13 v v in = 0 v ds = 25 v v in = 0 50 200 m a m a i iss supply current from input pin v ds = 0 v v in = 10 v 250 500 m a on ( * ) symbol parameter test conditions min. typ. max. unit v in(th) input threshold voltage v ds = v in i d + ii n = 1 ma 0.8 3 v r ds(on) static drain-source on resistance v in = 10 v i d = 5 a v in = 5 v i d = 5 a 0.1 0.14 w w dynamic symbol parameter test conditions min. typ. max. unit g fs ( * ) forward transconductance v ds = 13 v i d = 5 a 6 8 s c oss output capacitance v ds = 13 v f = 1 mhz v in = 0 350 500 pf vnp10n07 2/11
electrical characteristics (continued) switching ( ** ) symbol parameter test conditions min. typ. max. unit t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd = 15 v i d = 5 a v gen = 10 v r gen = 10 w (see figure 3) 50 80 230 100 100 160 400 180 ns ns ns ns t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd = 15 v i d = 5 a v gen = 10 v r gen = 1000 w (see figure 3) 600 0.9 3.8 1.7 900 2 6 2.5 ns m s m s m s (di/dt) on turn-on current slope v dd = 15 v i d = 5 a v in = 10 v r gen = 10 w 60 a/ m s q i total input charge v dd = 12 v i d = 5 a v in = 10 v 30 nc source drain diode symbol parameter test conditions min. typ. max. unit v sd ( * ) forward on voltage i sd = 5 a v in = 0 1.6 v t rr ( ** ) q rr ( ** ) i rrm ( ** ) reverse recovery time reverse recovery charge reverse recovery current i sd = 5 a di/dt = 100 a/ m s v dd = 30 v t j = 25 o c (see test circuit, figure 5) 125 0.3 4.8 ns m c a protection symbol parameter test conditions min. typ. max. unit i lim drain current limit v in = 10 v v ds = 13 v v in = 5 v v ds = 13 v 7 7 10 10 14 14 a a t dlim ( ** ) step response current limit v in = 10 v v in = 5 v 20 50 30 80 m s m s t jsh ( ** ) overtemperature shutdown 150 o c t jrs ( ** ) o vertemperature reset 135 o c i gf ( ** ) fault sink current v in = 10 v v ds = 13 v v in = 5 v v ds = 13 v 50 20 ma ma e as ( ** ) single pulse avalanche energy starting t j = 25 o c v dd = 20 v v in = 10 v r gen = 1 k w l = 10 mh 0.4 j ( * ) pulsed: pulse duration = 300 m s, duty cycle 1.5 % ( ** ) parameters guaranteed by design/characterization vnp10n07 3/11
during normal operation, the input pin is electrically connected to the gate of the internal power mosfet. the device then behaves like a standard power mosfet and can be used as a switch from dc to 50 khz. the only difference from the user?s standpoint is that a small dc current (i iss ) flows into the input pin in order to supply the internal circuitry. the device integrates: - overvoltage clamp protection: internally set at 70v, along with the rugged avalanche characteristics of the power mosfet stage give this device unrivalled ruggedness and energy handling capability. this feature is mainly important when driving inductive loads. - linear current limiter circuit: limits the drain current id to ilim whatever the input pin voltage. when the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold t jsh . - overtemperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. the location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. overtemperature cutout occurs at minimum 150 o c. the device is automatically restarted when the chip temperature falls below 135 o c. - status feedback: in the case of an overtemperature fault condition, a status feedback is provided through the input pin. the internal protection circuit disconnects the input f rom the gate and connects it instead to ground via an equivalent resistance of 100 w . the failure can be detected by monitoring the voltage at the input pin, which will be close to ground potential. additional features of this device are esd protection according to the human body model and the ability to be driven from a ttl logic circuit (with a small increase in r ds(on) ). protection features vnp10n07 4/11
thermal impedance output characteristics static drain-source on resistance vs input voltage derating curve transconductance static drain-source on resistance vnp10n07 5/11
static drain-source on resistance capacitance variations normalized on resistance vs temperature input charge vs input voltage normalized input threshold voltage vs temperature normalized on resistance vs temperature vnp10n07 6/11
turn-on current slope turn-off drain-source voltage slope switching time resistive load turn-on current s lope turn-off drain-source voltage slope switching time resistive load vnp10n07 7/11
switching time resistive load step response current limit current limit vs junction temperature source drain diode forward characteristics vnp10n07 8/11
fig. 2: unclamped inductive waveforms fig. 3: switching times test circuits for resistive load fig. 4: input charge test circuit fig. 1: unclamped inductive load test circuits fig. 5: test circuit for inductive load switching and diode recovery times fig. 6: waveforms vnp10n07 9/11
10 /1 1 vnp10n07 dim. mm. min. typ max. a 4.40 4.60 b 0.61 0.88 b1 1.15 1.70 c 0.49 0.70 d 15.25 15.75 e 1 0 10.40 e 2.40 2.70 e1 4.95 5.15 f 1.23 1.32 h1 6.20 6.60 j1 2.40 2.72 l13 14 l1 3.50 3.93 l20 16.40 l30 28.90 ? p 3.75 3.85 q 2.65 2.95 package weight 1.9gr. (typ.) to-220 mechanical data
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